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Figure 3 (a) compares presynthesis RTL power estimation values resulting from RTPow to the postsynthesis power figures coming from DesignPower, for the first two circuits (% difference). In Figure 3 (b), the processor core (uP) has been tested under two realistic patterns of input stimuli traced from a high level system simulation.

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In the C55x processor on the other hand, the TCC connects to the main core via a dedicated port, through which it has access to the processor memory and register file (Figure ). The main instruction decode pipeline of the processor sends control information to the TCC when it encounters a coprocessor instruction during program execution.

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